4-241 fast and ls ttl data product preview octal transceiver/register with 3-state outputs these devices consist of bus transceiver circuits with 3-state d-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. data on the a or b bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. output enable (oe ) and dir pins are provided to control the transceiver function. in the transceiver mode, data present at the high impedance port may be stored in either the a or the b register or in both. the select controls can multiplex stored and real-time (transparent mode) data. the direction control determines which bus will receive data when the enable oe is active low . in the isolation mode (oe high), a data may be stored in the b register and/or b data may be stored in the a register. ? independent registers for a and b ? multiplexed real-time and stored data ? choice of true (f646) and inverting (f648) data paths ? 3-state outputs pin assignments 22 21 20 19 18 17 1 2 3 4 5 6 7 24 23 8 v cc cpab cpba sba oe b 0 b 2 b 1 b 3 sab dir a 0 a 1 a 2 a 3 a 4 9 10 11 12 a 5 a 6 a 7 gnd 16 15 14 13 b 4 b 6 b 5 b 7 f646 22 21 20 19 18 17 1 2 3 4 5 6 7 24 23 8 v cc cpab cpba sba oe b 0 b 2 b 1 b 3 sab dir a 0 a 1 a 2 a 3 a 4 9 10 11 12 a 5 a 6 a 7 gnd 16 15 14 13 b 4 b 6 b 5 b 7 f648 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 f646 cpab sab dir cpba sba oe a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 f648 cpab sab dir cpba sba oe logic symbols 1 2 3 23 22 21 20 19 18 17 16 15 14 13 4 5 6 7 8 9 10 11 20 19 18 17 16 15 14 13 1 2 3 23 22 21 4 5 6 7 8 9 10 11 this document contains information on a product under development. motorola reserves the right to change or discontinue this product without notice. mc54/74f646 mc54/74f648 octal transceiver/register with 3-state outputs fast ? schottky ttl ordering information mc54fxxxj ceramic mc74fxxxn plastic mc74fxxxdw soic n suffix plastic case 724-03 dw suffix soic case 751e-03 24 1 24 1 j suffix ceramic case 758-01 24 1
4-242 fast and ls ttl data mc54/74f646 ? mc54/74f648 function table inputs data i/o* operation/function oe bar dir cpab cpba sab sba a 0 a 7 b 0 b 7 operation/function h h h h x x x x h or l x h or l x x x x x x x x x input input input input input input input input isolation store a n data in a register store b n data in b register store a n /b n data in a/b register l l l l h h h h x h or l x x x x l l h h x x x x input input input input output output output output a n to b n e real time (transparent mode) store a n data in a register a register to b n (stored mode) clock a n data to b n and into a register l l l l l l l l x x x x x h or l x x x x l l h h output output output output input input input input b n to a n e real time (transparent mode) store b n data in b register b register to a n (stored mode) clock a n data to b n and into b register *the data output function may be enabled or disabled by various signals at the oe bar and dir inputs. data input functions are always enabled; i.e., data at the * bus pins will be stored on every low-to-high transition of the appropriate clock inputs. h = high voltage level l = low voltage level x = don't care = low-to-high transition guaranteed operating ranges symbol parameter min typ max unit v cc dc supply voltage 54, 74 4.5 5.0 5.5 v t a operating ambient temperature range 54 74 55 0 25 25 125 70 c i oh output current ? high 54 74 e e e e 12 15 ma i ol output current ? low 54 74 e e e e 48 64 ma
4-243 fast and ls ttl data mc54/74f646 ? mc54/74f648 to 7 other channels a 0 b 0 oe dir cpba sba cpab sab d 0 c 0 d 0 c 0 1 of 8 channels logic diagram f646
4-244 fast and ls ttl data mc54/74f646 ? mc54/74f648 to 7 other channels a 0 b 0 oe dir cpba sba cpab sab d 0 c 0 d 0 c 0 1 of 8 channels logic diagram f648
4-245 fast and ls ttl data mc54/74f646 ? mc54/74f648 dc characteristics over operating temperature range (unless otherwise specified) limits test conditions (note 1) symbol parameter min typ max unit test conditions (note 1) v ih input high voltage 2.0 e e v guaranteed as a high signal v il input low voltage e e 0.8 v guaranteed as a low signal v ik input clamp diode voltage e e 1.2 v v cc = min, i in = 18 ma v oh output high voltage a n , b n 54/74 2.4 e e v i oh = 3.0 ma v cc = 4.5 v v oh output high voltage a n , b n 74 2.7 e e v i oh = 3.0 ma v cc = 4.75 v v oh output high voltage a n , b n 54 2.0 e e v i oh = 12.0 ma v cc = 4.5 v 74 2.0 e e v i oh = 15.0 ma v cc = 4.5 v v ol output low voltage a n , b n 54 e e 0.55 v i ol = 48 ma v cc = min v ol output low voltage a n , b n 74 e e 0.55 v i ol = 64 ma v cc = min i ih input high current non i/o pins e e 20 m a v cc = max, v in = 2.7 v i ih input high current non i/o pins e e 100 m a v cc = max, v in = 7.0 v ih i/o (aa, bn) e e 1.0 ma v cc = max, v in = 5.5 v i il input low current non i/o pins e e 600 m a v cc = max, v in = 0.5 v i ih + i ozh output leakage current i/o (a n , b n ) e e 70 m a v cc = max v out = 2.7 v i il + i ozl output leakage current i/o (a n , b n ) e e 650 m a v cc = max, v out = 0.5 v i os output short circuit current (note 2) 100 e 225 ma v cc = max, v out = gnd i cc power supply current i cch e e 135 v out = high i cc power supply current i ccl e e 150 ma v out = low v cc = max cc i ccz e e 150 v out = high z notes: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. not more than one output should be shorted at a time, nor for more than 1 second.
4-246 fast and ls ttl data mc54/74f646 ? mc54/74f648 ac electrical characteristics 54/74f 54f 74f t a = +25 c v cc = +5.0 v c l = 50 pf r l = 500 w t a = 55 c to +125 c v cc = +5.0 v 10% c l = 50 pf r l = 500 w t a = 0 c to +70 c v cc = +5.0 v 10% c l = 50 pf r l = 500 w symbol parameter min max min max min max unit f max maximum clock frequency 100 e 75 e 90 e mhz t plh t phl propagation delay clock to bus 2.0 2.0 7.0 8.0 2.0 2.0 8.5 9.5 2.0 2.0 8.0 9.0 ns t plh t phl propagation delay bus to bus (f646) 1.0 1.0 7.0 6.5 1.0 1.0 8.0 8.0 1.0 1.0 7.5 7.0 ns t plh t phl propagation delay bus to bus (f648) 1.0 1.0 7.0 6.5 1.0 1.0 10.0 9.0 1.0 1.0 7.5 7.0 ns t plh t phl propagation delay sba or sab to a n or b n 2.0 2.0 7.5 7.5 2.0 2.0 10.0 10.0 2.0 2.0 9.0 9.0 ns t pzh t pzl output enable time oe to a n or b n 2.0 2.0 7.0 7.0 2.0 2.0 9.5 9.5 2.0 2.0 8.5 8.5 ns t phz t plz output disable time oe to a n or b n 1.0 2.0 7.0 7.0 1.0 2.0 9.5 9.5 1.0 2.0 8.5 8.5 ns t pzh t pzl output enable time dir to a n or b n 2.0 2.0 7.0 7.0 2.0 2.0 9.5 9.5 2.0 2.0 8.5 8.5 ns t phz t plz output disable time dir to a n or b n 1.0 2.0 7.0 7.0 1.0 2.0 9.5 9.5 1.0 2.0 8.5 8.5 ns ac operating requirements 54/74f 54f 74f t a = +25 c v cc = +5.0 v c l = 50 pf r l = 500 w t a = 55 c to +125 c v cc = +5.0 v 10% c l = 50 pf r l = 500 w t a = 0 c to +70 c v cc = +5.0 v 10% c l = 50 pf r l = 500 w symbol parameter min max min max min max unit t s(h) t s(l) setup time, high or low bus to clock 4.0 4.0 e e 5.0 5.0 e e 5.0 5.0 e e ns t h(h) t h(l) hold time, high or low bus to clock 0.0 0.0 e e 0.0 0.0 e e 0.0 0.0 e e ns t w(h) t w(l) clock pulse width high or low 4.0 5.0 e e 4.0 5.0 e e 4.0 5.0 e e ns
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